L64105 LSI Logic Corporation, L64105 Datasheet - Page 193

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.9
SDRAM Access
Write DMA SDRAM Source Address
DMA Read 8 Bytes from 194
& Decrement Transfer Count
No
No
No
218[2:0] = [18:16]
217 = [15:8]
216 = [7:0]
(LSB must be set last)
Pause for 1 Clock Cycle
193[2:1] = 01 - Read
Read FIFO Full?
Set DMA Mode
DREQ_N = 0?
Read
192[5] = 1?
Count = 0?
Transfer
DMA SDRAM Read/Write Flowchart
DMA
Yes
Yes
Yes
Set DMA Transfer Byte Ordering
DMA Controller Operations
193[6] = DMA Endian
193[2:1] = 0b00 Idle
193[2:1] = 0b00 Idle
Set DMA Mode
Set DMA Mode
Begin
Done
Write DMA SDRAM Target Address
& Decrement Transfer Count
DMA Write 8 Bytes to 195
Pause for 1 Clock Cycle
215[2:0] = [18:16]
214 = [15:8]
213 = [7:0]
(LSB must be set last)
193[2:1] = 10 - Write
Write FIFO Empty?
Set DMA Mode
DREQ_N = 0?
Yes
Yes
Yes
192[6] = 1?
Count = 0?
Transfer
DMA
Write
No
No
No
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