L64105 LSI Logic Corporation, L64105 Datasheet - Page 128

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.64
Figure 4.65
4-46
Reg. 213
Reg. 214
Reg. 215
Reg. 216
Reg. 217
Reg. 218
MSB
MSB
LSB
LSB
7
7
Registers 213–215 (0xD5–0x0D7)DMA SDRAM Target Address [18:0]
Registers 216–218 (0xD8–0x0DA) DMA SDRAM Source Address [18:0]
Registers 207–212, and 222 and 223
testing the Phase-Locked Loop (PLL). The PLL test is run by setting bit
0, PLL Test, in Register 204
can be read from Register 221,
detector and the VCO. The PLL passes the test if the frequency of the
PLL falls between the high frequency value and the low frequency value.
The PLL test interrupts the system clock and should not be attempted
when the chip is running.
During DMA Write and Block Move, the DMA SDRAM Target Address is
the starting address where future DMA writes will take place. This
address is automatically incremented after a 64-bit word is transferred to
SDRAM from the internal 8 x 64 write FIFO. The DMA SDRAM Target
Address should be updated by the host only when the write FIFO is
empty.
During DMA Read and Block Move, the DMA SDRAM Source Address
is the starting address where future DMA reads will take place. This
address is automatically incremented after a 64-bit word is transferred
from SDRAM to the internal 8 x 64 read FIFO. The DMA SDRAM Source
Register Descriptions
Note:
DMA SDRAM Target Address (DMA + block) [15:8]
DMA SDRAM Target Address (DMA + block) [7:0]
DMA SDRAM Source Address (dma+block) [15:8]
Reserved
Reserved
DMA SDRAM Source Address (dma+block) [7:0]
Registers 207 through 212 are included for LSI Logic’s
testing purposes. Do not write to the registers without
specific directions from LSI Logic.
R/W
R/W
R/W
R/W
(page
(page
3
3
4-43). The results from the PLL test
(page
4-47.) Tests are run on the phase
4-47) set the parameters for
DMA SDRAM Source Address
DMA SDRAM Target Address
2
2
(DMA + block) [18:16] R/W
(DMA + block) [18:16] R/W
0
0