L64105 LSI Logic Corporation, L64105 Datasheet - Page 205

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

6.3 Preparser
6.3.1 Host Selection of Streams and Headers
For A/V PES and program streams, the Preparser strips the packets of
headers and writes the headers and packet data payloads into separate
buffer areas in the off-chip SDRAM memory. The host writes the start
and end addresses of each of the buffer areas into registers. The internal
microcontroller transfers these addresses to the Buffer Controller. The
Buffer Controller maintains current read and write pointers for each buffer
area defined. When the Preparser strips an item out of the bitstream, the
microcontroller gets the current write pointer to the buffer area for that
item and writes the item into the buffer. The microcontroller also writes
the LSB of the item’s address pointer to the appropriate register. If the
host reads the LSB, the Buffer Controller writes the next pointer address
byte and the MSB to the register. The Buffer Controller and the host
registers used to program these buffer areas are explained in detail in
Section 6.4, “Channel Buffer Controller,” page
The host has control over which streams are preparsed and if headers
are stored. The register bits that define the preparse operation are
discussed here. It is assumed in the Preparser descriptions that follow
that the particular stream and header has been selected or enabled.
The host selects the video stream to be decoded by setting the Video
Stream Select Enable bits in Register 145 and entering a 4-bit Video
Stream ID in the same register
Enable codes are listed in
Table 6.2
Preparser
Video Stream
Select Enable
0b00
0b01
0b10
0b11
Video Stream Select Enable Bits
Description
Discard all video packets
MPEG ID selected
All Video Stream IDs stored
Discard all video packets
Table
(page
6.2.
4-35). The Video Stream Select
6-27.
6-9