L64105 LSI Logic Corporation, L64105 Datasheet - Page 105

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.24
Figure 4.25
Reg. 74
Reg. 75
Reg. 76
Reg. 77
MSB
MSB
LSB
LSB
Registers 74 and 75 (0x04A and 0x04B) Video ES Channel Buffer End
Address [13:0]
Registers 76 and 77 (0x04C and 0x04D) Audio ES Channel Buffer Start
Address [13:0]
7
7
Reserved
Reserved
Interface of the L64105 converts the address to an SDRAM address at
a 256-byte boundary in SDRAM. This register should only be updated
while the channel is stopped (reset).
These registers allow the host to program the Video ES channel buffer
end address. The address is entered as if it were the upper 14 bits of a
21-bit address for a conventional 2M x 16 RAM address. The Memory
Interface of the L64105 converts the address to an SDRAM address at
a 256-byte boundary in SDRAM. This register should only be updated
while the channel is stopped (reset).
These registers allow the host to program the Audio ES channel buffer
start address. The address is entered as if it were the upper 14 bits of a
21-bit address for a conventional 2M x 16 RAM address. The Memory
Interface of the L64105 converts the address to an SDRAM address at
a 256-byte boundary in SDRAM. This register should only be updated
while the channel is stopped (reset).
Video Decoder Registers
6
6
Audio ES Channel Buffer Start Address [7:0]
Video ES Channel Buffer End Address [7:0]
5
5
Audio ES Channel Buffer Start Address [13:8]
Video ES Channel Buffer End Address [13:8]
R/W
R/W
R/W
R/W
0
0
4-23