L64105 LSI Logic Corporation, L64105 Datasheet - Page 97

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.12
Figure 4.13
7
7
Reserved
Register 18 (0x012)
Register 19 (0x013)
Capture on Audio PES Ready
Capture on Video PES Ready
Reserved
Capture on DTS Video
Capture on DTS Audio
Reserved
Audio Start on Compare
Host Interface Registers
5
Reserved
When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Audio PES Ready.
When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Video PES Ready.
Clear these bits when writing to this register.
When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects
Decode Time Stamp (DTS) Video.
When this bit is set and the L64105 is in the Capture
Mode, the SCR Counter value is captured and written to
Registers 13 through 16 when the preparser detects DTS
Audio.
Clear these bits when writing to this register.
When the L64105 is in the Compare Mode, setting this
bit generates a single-cycle, autostart pulse for starting
the Audio Decoder when the current value of the SCR
Counter is equal to the value in the SCR Compare Audio
Capture on
DTS Audio
4
Capture on
DTS Video
3
2
2
on Compare
Video Start
Reserved
1
on Compare
Audio Start
R/W 6
R/W 7
R/W 3
R/W 4
R/W 0
0
0
[2:0]
[7:5]
4-15