L64105 LSI Logic Corporation, L64105 Datasheet - Page 348

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.5.2 Synchronization
Figure 10.5 Linear PCM Audio Sample Syntax
10-16
MSB
16 bits
(ch 0)
A_2n
The upper 16 bits of sample of each channel
LSB
S_2n
(ch 1)
B_2n
The Preparser in the Channel Interface substitutes the original
substream Linear PCM ID with an 8-byte sync word to mark the
beginning of each Linear PCM packet. The Linear PCM Decoder
searches for and synchronizes to the sync word. If the decoder loses
synchronization, it sets the Audio Sync Error Interrupt bit in Register 4
(page
mutes the audio output, and searches for the next sync word.
Linear PCM bitstream samples can be 16, 20 or 24 bits as shown in
Figure
and the lower 4 or 8 bits. The output PCM samples to the DAC interface
can be 16, 20, or 24 bits in length. On the other hand, the S/P DIF
interface accepts only 16-bit samples. The last 4 or 8 bits of 20- or 24-bit
samples are truncated for the S/P DIF interface.
The host can override the bitstream sample resolution for the decoder by
setting the Overwrite Quantization bit in Register 366
programming the Host Quantization bits in the same register for 16-,
20-, or 24-bit samples. The decoder truncates or extends the samples
accordingly.
Audio Decoder Module
16-bit mode
4-8), asserts INTRn to the host if the interrupt is not masked,
10.5. Twenty or 24-bit samples are divided into the upper 16 bits
(ch 3-7)
20-bit/24-bit mode
/8 bits(24-bit mode)
4 bits(20-bit mode)
MSB
S_2n+1
(ch 0)
a_2n b_2n
LSB
(ch 1)
(ch 8)
H_2n
sample data of each channel
E_2n
The lower 4 or 8 bits of
(ch 3-7)
E_2n+1
(page
4-89) and
(ch 8)
h_2n