L64105 LSI Logic Corporation, L64105 Datasheet - Page 199

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 6.1
CH_DATA[7:0]
6.2 Interface Signals Operation
( 9 MHz)
(27 MHz)
VVALIDn
AVALIDn
SYSCLK
VREQn
AREQn
DCK
Channel Interface
L64105 Decoder
Channel Interface Block Diagram
Channel
Input
FIFO
The L64105’s Channel Interface can be connected to a variety of
devices. The interface is capable of accepting one byte of data in 3Tc
time (Tc = 1/27 MHz = 37 ns). This provides a transfer rate of nine
Mbytes/s. The interface can be configured for asynchronous or
synchronous mode with the Channel Request Mode bit in Register 5
(page
channel data bytes are paced into the L64105 with the REQ and VALID
signals. In synchronous mode, the DCK input from the connecting device
is used by the L64105 to gate the REQ signals and is gated by the VALID
signals. The gated DCK strobes the data bytes into the channel input
FIFO.
Interface Signals Operation
Synchronizer
Interface
System
Host
4-9). In asynchronous mode, the DCK input pin is tied to VSS and
64-bit Data Bus
Address Bus
Synchronizer
Video
Layer
PLL
81 MHz Clock
Preparser
Controller
Buffer
Microcontroller
Channel
Write
FIFO
Interface
Memory
D[15:0]
Control
A[11:0]
1 M x 16
2 M x 16
SDRAM
or
6-3