L64105 LSI Logic Corporation, L64105 Datasheet - Page 179

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.2
DTACKn
READ
D[7:0]
A[8:0]
CSn
DSn
ASn
Motorola Mode Write Timing
Table 5.1
Figure 5.2
cycle. The host asserts the chip select (CSn) signal to inform the L64105
that it wishes to read or write. The host then drives READ low to signal
that it is a write cycle and asserts ASn to strobe the address onto the
interface address bus, A[8:0].
When the L64105 detects CSn active, it drives its DTACKn output high
to inform the host that it is not ready for a read or write and low when it
is ready. In the example shown, the decoder initially set DTACKn high to
delay the cycle. After DTACKn goes low and if the data is stable, the host
deasserts DSn to strobe the data into the decoder.
Interface Signals
Signal
READ/READn
DTACKn/RDYn Output (3-state)
WAITn/WTN
INTRn
DREQn
PREQn
shows the interface signal timing for a Motorola mode write
Host Interface Signals (Cont.)
L64105 Direction
Input
Output (3-state)
Output (open drain) INTRn
Output
Output
Intel Mode
READn
RDYn
WTN
DREQn
PREQn
Motorola Mode
READ
DTACKn
WAITn
INTRn
DREQn
PREQn
5-3