L64105 LSI Logic Corporation, L64105 Datasheet - Page 263

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

8.2.15 User Data FIFO Operation
When the first data byte is written to the FIFO, it is placed in the Aux
Data FIFO Output register. At the same time, the Postparser writes the
layer ID of the data byte into the Auxiliary Data Layer ID field of Register
64 (see
data. As soon as the data byte is read, the two registers are updated if
another unread byte is available in the FIFO.
Table 8.14
When the host writes a 1 to bit 0 of Register 64, the read and write
pointers of the Aux Data FIFO are reset and the FIFO’s status goes to
empty. Any previously unread bytes in the FIFO will be overwritten and
lost when new data is written into the FIFO.
User Data FIFO operation is very much like Aux Data FIFO operation. In
fact, they share some interrupt bits. The complete description, however,
is given here for your convenience and not referenced back to the
previous section.
The User Data FIFO is used to buffer user data parsed from the
bitstream to the host. The User Data FIFO is 128 bytes deep and
operates as a circular buffer. Since the decoder parses user data at
8 bits/cycle, the FIFO can fill up very quickly when large amounts of user
data are in the channel. The various registers associated with the User
Data FIFO are listed in
More complete descriptions can be found at the page references shown
in the table.
Postparser Operation
Bits 64[4:2]
0b000
0b001
0b010
0b111
Table
Auxiliary Data Layer ID Assignments
8.14). The host should read the ID first and then read the
Layer
Sequence
Group of pictures
Picture
Extension layer (picture or sequence)
Table 8.15
and described in the text following.
8-21