L64105 LSI Logic Corporation, L64105 Datasheet - Page 89

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.4
Read
Write
Register 3 (0x003)
7
Reserved
Reserved
Audio ES Channel Buffer Overflow Interrupt
Video ES Channel Buffer Overflow Interrupt
Reserved
Audio ES Channel Buffer Underflow Interrupt
Video ES Channel Buffer Underflow Interrupt
Reserved
Host Interface Registers
6
Underflow
Underflow
Video ES
Video ES
Channel
Interrupt
Channel
Buffer
Buffer
Mask
the INTRn output signal. The interrupt is used for
audio/video synchronization.
This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
This bit is set and INTRn is asserted (if not masked)
when the Audio ES channel buffer in SDRAM overflows.
The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
This bit is set and INTRn is asserted (if not masked)
when the Video ES channel buffer in SDRAM overflows.
The bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
Set these bits when writing to this register.
This bit is set and INTRn is asserted (if not masked)
when the Audio ES channel buffer in SDRAM underflows
(becomes empty). The bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.
This bit is set and INTRn is asserted (if not masked)
when the Video ES channel buffer in SDRAM underflows
(becomes empty). The bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.
Set these bits when writing to this register.
5
Underflow
Underflow
Audio ES
Audio ES
Channel
Interrupt
Channel
Buffer
Buffer
Mask
4
3
Reserved
Reserved
2
Video ES
Video ES
Overflow
Overflow
Interrupt
Channel
Channel
Buffer
Buffer
Mask
1
Audio ES
Audio ES
Overflow
Overflow
Channel
Interrupt
Channel
Buffer
Buffer
Mask
0
[2:3]
[7:6]
4-7
0
1
4
5