L64105 LSI Logic Corporation, L64105 Datasheet - Page 134

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.78
4-52
Read
Write
Register 238 (0x0EE)
7
Reserved
Reserved
Video Continuous Repeat Frame Mode
Reserved
Rip Forward Mode Status
Rip Forward Mode Enable
Register Descriptions
6
Current Decode Frame
This bit controls the behavior of the video repeat frame
function. When cleared, one frame is repeated and then
the Video Repeat Frame Enable bit is cleared by the
microcontroller. When this bit is set, frames are repeated
continuously until the host clears the Video Repeat
Frame Enable bit to end the operation.
Indicates the status of the Rip Forward Mode as
described for the enable bit following.
Setting this bit enables the Rip Forward Mode. In this
mode, the decoder processes pictures as fast as it can
without regard to the status of the display, i.e., the rate
control for the decode with respect to the vertical sync of
the display is turned off. The rate control for the decode
is governed by the Rip Forward Display Single Step
Command (bit 1 in this register). The microcontroller
monitors the single step command bit after it has
received a picture start code and processed a picture
header. The decode for that picture only proceeds if the
single step command bit is set. The single step command
bit is cleared on reading by the microcontroller. Rip
Forward Mode is intended to be used in an application
where not every picture that is decoded needs to be
displayed. The picture to be displayed is specified in
separate registers. These registers are decoded in the
Video Interface module. (See Register 265 bits 4 and 5,
Display Override Mode, and Registers 285, 286, 287, and
288, Override Display Start Addresses for luma and
5
[1:0]
4
Read Only
Current Display Frame
3
[1:0]
2
Rip Forward
Rip Forward
Single Step
Single Step
Command
Display
Display
Status
1
Rip Forward
Rip Forward
Enable
Status
Mode
Mode
0
[7:2]
W 1
W 0
R 0