L64105 LSI Logic Corporation, L64105 Datasheet - Page 169

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 4.4
Figure 4.129 Register 365 (0x16D)
ACLK Divider
Select [3:0]
0xD
0xE
0xF
Overwrite
Copyright
IEC -
7
IEC - Host
ACLK Divider Select [3:0] Code Definitions (Cont.)
Copyright
ACLK
Input
512 * 48
512 * 48
256 * 48
6
LPCM - Dynamic Range On
Reserved
Reserved
IEC - Host Emphasis [2:0]
IEC - Overwrite Emphasis
IEC - Host Copyright
Audio Decoder Registers
Emphasis
Overwrite
S/P DIF Interface BCLK DAC Interface BCLK DAC A_ACLK
128 * 32 = ACLK
128 * 32 = ACLK
128 * 32 = ACLK
IEC -
5
Setting this bit in Linear PCM Mode enables the dynamic
range feature of the Linear PCM bitstream. When the bit
is cleared, dynamic range control is off and the PCM
samples recovered from the bitstream are not multiplied
by the gain value. The default value of this bit is 0.
Clear these bits when writing to this register.
Clear these bits when writing to this register.
When the overwrite emphasis bit (bit 5 in this register) is
set, the value in the host emphasis field is used instead
of the emphasis value in the bitstream.
When this bit is set, the value in bits [4:2] of this register
are used instead of the emphasis value in the bitstream.
The default value of this bit is 0.
When the overwrite copyright bit (bit 7 in this register) is
set, the value of the Host Copyright bit is used instead of
the copyright value in the bitstream. The default value of
this bit is 0.
4
IEC - Host Emphasis [2:0]
6
6
3
64 * 32 = ACLK
64 * 32 = ACLK
64 * 32 = ACLK
2
12
12
6
256 * 32 = ACLK
384 * 32 = ACLK
256 * 32 = ACLK
1
Reserved
R/W [4:2]
R/W 4
R/W 5
R/W 6
0
[7:5]
[1:0]
4-87
3
2
1