L64105 LSI Logic Corporation, L64105 Datasheet - Page 92

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.7
4-10
7
Register 6 (0x006)
Channel Pause
Channel Bypass Enable
AREQ Status
VREQ Status
Reserved
Clear Interrupt Pin
Register Descriptions
synchronous with the external device clock (DCK), then
the Channel Request Mode bit needs to be set. In this
mode, the channel internal request is sampled twice, first
by the rising edge of internal DCK and then by the falling
edge of internal DCK, before being sent out as a REQn
signal.
Setting this bit prevents the channel request signals
(AREQn and VREQn) from being asserted so channel
data is not transferred into the L64105. The external host
must clear this bit to reassert the REQn signals.
Setting this bit allows the host to write data directly to the
channel, bypassing the parallel channel input port. Video
ES or Audio ES channel data can be written into
Registers 28 or 29 respectively
mode. At reset, this register defaults to 0, i.e., no bypass.
This bit is set when the AREQn signal in the chip is
asserted. This bit position is read only.
This bit is set when the VREQn signal in the chip is
asserted. This bit position is read only.
This bit is used to clear the interrupt signal, INTRn, of
previous pending interrupts. In normal operation, events
in the L64105 can cause INTRn to be asserted if the
event mask is cleared. The bits in the interrupt registers
(Registers 0 through 4) are cleared when read by the
host. However, INTRn remains asserted until all the
interrupt registers are read (all bits cleared) and the Clear
Interrupt Pin bit is set.
Reserved
(page
4-16) when in this
1
Interrupt Pin
Clear
R/W 2
R/W 3
0
[7:6]
W 0
R 4
R 5