L64105 LSI Logic Corporation, L64105 Datasheet - Page 421

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

bitstream sample override 10-12,
bitstream sample resolution
bitstream searches
bitstream syntax MPEG compressed
black backgrounds 9-13,
blank output 2-8,
BLANK signal
blanking
blanking intervals 9-7,
block diagram
description
usage overview 9-2,
interrupt handling
offset values 4-70,
vertical change
interrupt
A/V decoding system
A/V PES mode channel interface flowchart
A/VREQn circuits
audio decoder
audio encoding process
AVALIDn input synchronization circuit
block move flowchart
burst payload-length
channel interface
display area
DMA SDRAM read/write flowchart
elementary stream buffering
force rate control in rip forward mode
frame repeat modes
frame store organization-normal mode
horizontal pan and scan
horizontal pan and scan calculation
host interface
host read/write flowchart
I/O signals
IEC958 syntax
interrupt structure
ISO system stream
L64105 A/V decoder
linear PCM audio sample syntax
linear PCM output ports
memory interface
MPEG audio bitstream syntax
MPEG audio decoding flow
MPEG audio packet structure
MPEG data syntax IEC958 format
MPEG formatter pause bursts
MPEG macroblock structure
parsing an A/V PES transport stream
PES packet structure
PLLVDD decoupling circuit
preparsing an MPEG-1 system stream
9-2
4-5
2-8
2-8
2-2
9-6
9-2
5-2
10-4
10-31
9-8
4-56
6-3
9-40
6-7
7-2
5-9
4-71
9-39
A-9
9-39
10-21
8-39
1-3
Index
5-19
9-28
1-2
6-15
A-8
10-19
9-35
10-3
5-13
2-11
10-13
6-13
A-3
A-9
10-16
10-11
10-23
10-16
A-5
5-17
10-20
9-35
8-46
6-24
6-6
8-31
6-16
6-31
block moves
block transfer count bits
blocks
BMP only bit
borders
broken link mode 4-54,
buffer controller 1-3, 6-9,
buffers
setting up rip forward/display override
single skip display freeze
system clock reference
typical sequence of pictures in bitstream order
typical sequence of pictures in display order
video decoder
video interface
VVALIDn input synchronization circuit
DMA 4-40,
DMA flowchart
DMA host directed
DMA SDRAM source address
DMA SDRAM target address
read/write
SDRAM
SDRAM caution
SDRAM transfer count
basic unit
contiguous OSD storage and
See also channel buffer controller
A/V ES channel end addresses 6-13,
A/V ES channel start addresses 6-13,
A/V read compare enable
audio byte alignment
audio ES channel
audio ES channel end addresses 4-24,
audio ES channel reset
audio ES channel start addresses
audio ES channel write pointer addresses
audio ES DTS compare
audio flushes
audio PES header/system
auxiliary data FIFO 8-2,
auxiliary data FIFO status
complete
channel end addresses
channel start addresses 4-25,
channel writes 6-10,
layer ID assignments
layer origin
output
overflow
ready
reset
status
9-13
5-18
4-17
4-2
4-17
A-6
9-27
4-19
1-3
5-14
8-20
4-3
4-80
8-3
4-18
9-3
5-19
5-18
10-8
5-18
8-43
4-43
4-12
6-27
4-43
5-7
4-20
6-12
8-19
4-29
8-21
8-37
4-21
8-20
4-25
4-46
9-28
to
4-46
8-21
7-8
4-23
7-8
6-6
8-42
7-8
10-7
4-26
A-6
A-6
IX-5