L64105 LSI Logic Corporation, L64105 Datasheet - Page 188

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.4.1.2 Host Write
5-12
The host write operation proceeds similarly to the host read operation.
The host begins an SDRAM write operation by setting or clearing the
Host SDRAM Byte Ordering bit (if necessary) to change the endian
mode and then writing the Host SDRAM Target Address, LSB last.
The host can then begin to write bytes to the Host SDRAM Write Data
register. The host can continue to write bytes to the write register as long
as the Host Write FIFO Full bit is not set.
The L64105 only writes data out of the host write FIFO when a complete
8-byte (64-bit) word is available.
When the host is finished with the current host SDRAM write operation,
it must wait for the Host Write FIFO Empty bit to be set before beginning
any new SDRAM operation (host r/w, DMA r/w, or block move.)
Note in
entered with the LSB last. Writing the LSB of the source or target
address causes the host read or write FIFO to reset, respectively. Also,
note that the FIFO status registers require 1 clock cycle to update. There
should be at least 1 clock cycle separating the last read/write command
and checking the FIFO status registers.
Host Interface
Caution:
Figure 5.8
If the host attempts to write less than eight bytes of data to
SDRAM, the data will not be transferred to SDRAM. The
host can continue to transfer blocks of eight bytes as long
as the Host Write FIFO Full bit is not set.
that the host source and target addresses must be