L64105 LSI Logic Corporation, L64105 Datasheet - Page 34

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2-4
READ/READn Read/Write Strobe - Read Indicator
DTACKn/RDYn
WAITn
INTRn
I/O Signal Descriptions
WRITEn - Intel Mode
The external host asserts WRITEn to start a write cycle.
READn must be HIGH during a write cycle, and CSn
must be LOW during a write cycle. The address is
registered on the falling edge of WRITEn. The data is
latched by the L64105 on the rising edge of WRITEn.
READ - Motorola Mode
The Motorola host asserts READ HIGH for a read cycle
and deasserts it for a write cycle. CSn must be asserted
to select the L64105.
READn - Intel Mode
The Intel host asserts READn and holds WRITEn
deasserted to perform a read cycle. The address is
registered on the falling edge of READn. CSn must be
asserted to select the L64105.
Data Acknowledge/Data Ready
DTACKn - Motorola Mode
The L64105 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. DTACKn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64105 deasserts
DTACKn before the cycle is completed.
RDYn - Intel Mode
The L64105 asserts this signal to indicate to the external
host that the current bus transaction (read or write) can
be completed. RDYn is 3-stated if CSn is not asserted.
The bus cycle is terminated if the L64105 deasserts
RDYn before the cycle is completed.
Wait
This signal may be used instead of DTACKn/RDYn by
hosts that require an inverted sense. The L64105 asserts
WAITn to indicate that its Host Interface is busy with a
read or write bus cycle and it deasserts it when the
current cycle is completed. WAITn is 3-stated when CSn
is not active.
Interrupt
INTRn is an active-LOW, open-drain, output signal. The
L64105 asserts this signal to alert the host that an
3-State Output
3-State Output
OD Output
Input