L64105 LSI Logic Corporation, L64105 Datasheet - Page 167

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.128 Register 364 (0x16C)
7
Reserved
User
Valid
ACLK Divider Select [3:0]
Audio Decoder Registers
5
LPCM - Dynamic
The value of the User bit to be packed in the IEC958
(S/P DIF) output. The default is 0.
The data Valid bit to be packed in the IEC958 (S/P DIF)
output. The bit is set when the S/P DIF output is from a
formatter in the Audio Decoder and is cleared when the
output is from one of the audio decoders.
The host sets these bits to select clock divider values
which derive the S/P DIF interface BCLK, DAC interface
BCLK, and external DAC A_ACLK from the selected
ACLK_ input (bits 0 and 1 in Register 363). The divider
values depend on ACLK_ availability, the input audio
sampling frequency (Fs), the sample resolution
(16/24/32 bits per sample), and the external DAC
capabilities. The L64105 supports sampling rates of 32,
44.1, and 48 kHz for MPEG, and 48 and 96 kHz for
Linear PCM. The equations for the derived clocks are:
S/P DIF BCLK = Fs * 32 bits per sample * 2 channels * 2
DAC BCLK
Ext DAC A_ACLK
The available divider settings are listed in
the following cases as selection criteria:
Range On
Case I: All of the ACLK_ inputs are available. Select
the ACLK_ which is a multiple of the input sampling
frequency using bits 0 and 1 in Register 363. Then
use the 0x0 through 0x4 ACLK Divider Select code
that matches the Fs-multiple of the ACLK_. For
example, if the input sampling frequency is 32 kHz
and ACLK_32 = 512 * 32 kHz, use the 0x2 ACLK
Divider Select code.
4
= Fs * 32 bits per sample * 2 channels
= Fs * 64
3
marks = Fs * 128
= Fs * 32 bits per sample * K
= Fs * 256 or Fs * 384
ACLK Divider Select [3:0]
Table
R/W [3:0]
4.4. Use
R/W 6
R/W 7
0
4-85