L64105 LSI Logic Corporation, L64105 Datasheet - Page 192

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.4.2.2 DMA Write
5-16
The DMA SDRAM write operation is very similar to the DMA SDRAM
read operation as shown in
Idle, sets the endian mode if necessary, writes the SDRAM target
address into the DMA SDRAM Target Address registers, and sets the
DMA Mode to Write. This causes the L64105 to assert the DREQn
signal.
The host’s DMA controller can then start writing bytes into the DMA
SDRAM Write Data register. Each set of eight bytes is loaded into the
DMA WrFIFO in the proper endian order. After the second 8-byte word
is in the WrFIFO, the L64105 SDRAM controller starts writing the words
to SDRAM as 16-bit words starting at the target address. The SDRAM
controller automatically increments the target address for each new
16-bit word.
Again, the DMA controller is responsible for maintaining the transfer
count. It continues to write bytes in as long as there is more than one
8-byte space left in the WrFIFO until the transfer count reaches zero. The
host must then wait until the DMA Write FIFO Empty bit is set and then
return the DMA Mode to Idle.
Host Interface
Caution:
The L64105 only writes data out of the DMA WrFIFO when
a complete 8-byte (64-bit) word is available. If the DMA
controller attempts to write less than eight bytes of data to
SDRAM or less than eight bytes in the last word, the data
is not transferred to SDRAM and is lost when the FIFO
pointers are next reset.
Figure
5.9. The host sets the DMA Mode to