L64105 LSI Logic Corporation, L64105 Datasheet - Page 121

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.54
Reserved
7
Byte Ordering
DMA Transfer
Register 193 (0x0C1)
6
Reserved
DMA Mode [1:0]
Memory Interface Registers
Refresh Extend [1:0]
5
Clear this bit when writing to this register.
Defines the state of the DMA Transfer Request (DREQn)
output signal per the following table.
DMA Mode
[1:0]
0b00
0b01
0b10
0b11
During DMA transfers, the external DMA controller should
use the DREQn output signal to determine whether or not
another 64-bit word can be transferred.
DMA Idle: This setting is used to hold DREQn
deasserted and prevent the external DMA controller from
transferring any data to or from SDRAM.
DMA Read: The on-chip SDRAM controller continuously
fills the internal 8 x 64-bit DMA read FIFO with data read
from the specified SDRAM source address. The SDRAM
address is automatically incremented until the read FIFO
is near full. Separate FIFOs and address registers are
available for DMA and host reads. The DMA controller
can retrieve the next available read byte from the DMA
SDRAM Read Data register (Register 219,
During DMA Read Mode, DREQn is asserted only when
there are more SDRAM data words in the read FIFO for
reading.
DMA Write: The DMA controller writes data to the DMA
SDRAM Write Data register (Register 220,
Every 8 bytes written are formed into a 64-bit word and
4
Host SDRAM
Transfer Byte
Ordering
Description
DMA Idle (DREQn = 1)
DMA Read (DREQn = read FIFO near empty)
DMA Write (DREQn = write FIFO near full)
Block Move (DREQn =1)
3
DMA Mode [1:0]
2
1
page
page
R/W [2:1]
Reserved
4-47).
4-47).
0
4-39
0