L64105 LSI Logic Corporation, L64105 Datasheet - Page 441

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

real-time decode
reconstructed pictures 2-7, 2-12, 6-29, 8-24, 9-30,
reconstruction (samples)
recovery bit (audio sync)
recovery mechanism
reduced memory frame store size PAL
Reduced Memory Mode (RMM)
reduced memory mode bit
reduced resolution
redundancy
refresh cycles 4-40,
refresh extend bits
registers
registers summary
repeat frame mode 4-62,
repeat frames
user data FIFO port
video items remaining
B pictures 8-43,
chroma frame stores
error detection
force rate control
interlaced modes
luma frame stores
output bus
portions
refreshes and
rip forward mode and
start command
tearing problems
display modes
segment select
video decoder
video interface
SDRAM timing
audio decoder
Aux data FIFO
host interface
memory interface
microcontroller
override
PCM FIFO mode
RAM test
resetting
user data FIFO
video decoder
video interface
video PES header channel buffer
video underflow control
continuous repeats
enable
status
summarized
4-51
4-51
9-34
9-14
4-73
2-11
4-91
2-8
4-62
7-7
4-2
4-41
8-32
4-72
4-17
8-33
4-78
9-19
4-48
4-58
7-5
4-57
8-19
4-69
9-20
3-1
4-40
8-22
5-5
9-19
7-5
4-54
8-43
8-31
10-26
8-49
4-38
7-9
4-52
to
to
4-19
7-9
Index
10-12
4-3
8-41
8-38
4-32
8-34
5-10
4-58
6-29
to
7-11
8-39
6-25
to
7-12
7-12
A-7
report end of test bit
reposition display modes
repositioning
request signals
requests
reset
RESETn signal
resolution 1-5, 1-7, 9-16,
resynchronize 6-7, 8-2,
revision number bits
rip forward display single step status bit
rip forward mode
RMM
ROM automated test
row address select (SDRAM)
A/V channel transfers
channel interface
channel mode set
current state
DMA transfers
external DMA controller
freeze
audio ES channel buffer
audio PES header/system channel buffer bit
Aux data FIFO bit
auxiliary data FIFO bit
channel bit
channel buffer 4-20,
channel buffers on error bit
chip
decoder
host FIFO buffers
microcontroller
pixel state
registers
software
timing
user data FIFO bit
video ES channel buffer bit
video PES header channel buffer bit
description
bitstream sample
enhancing 9-18,
raster mapper increment values
reduced
stereophonic digital programs
video decoder 8-48,
enable bit
single step command bit
single step status
status bit
See also reduced memory mode
B-7
usage overview
8-25
11-15
9-37
4-12
9-20
4-12
2-11
4-52
9-18
4-52
4-67
2-11
4-11
6-7
2-11
4-39
8-40
2-5
2-11
9-23
4-57
4-92
6-8
10-3
4-53
4-91
5-12
4-10
4-17
4-18
8-40
to
10-5
8-49
6-28
9-16
9-17
2-5
8-42
4-17
2-5
4-20
4-53
2-7
4-20
4-20
10-29
9-22
4-20
4-53
4-20
IX-25