L64105 LSI Logic Corporation, L64105 Datasheet - Page 125

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.59
Figure 4.60
Control for Programmable
Reg. 202
Reg. 203
MSB
LSB
Delay Path 2 [1:0]
7
Registers 202 and 203 (0x0CA and 0x0CB) Block Transfer Count [15:0]
Register 204 (0x0CC)
7
6
For an SDRAM block move, the host writes the number of 64-bit words
to be moved in these registers. During the move, these registers contain
the number of words left to transfer. These registers are not used during
a host SDRAM read/write. The Block Transfer Count defaults to 0xFFFF
at reset.
PLL Test
Reserved
Clk Out of Sync
Control for Programmable Delay Path 1 [1:0]
Memory Interface Registers
Control for Programmable
Delay Path 1 [1:0]
5
When this bit is set, it initiates the PLL test. Results are
stored in Register 221
Clear these bits when writing to this register.
When set, indicates that some of the 27-MHz and
81-MHz clocks are no longer synchronized. Used for
diagnostic purposes.
This register controls the selection of delay cells on the
81-MHz clock fed back from the SCLK pin.
Control Bits
0b00
0b01
0b10
0b11
4
Block Transfer Count [15:8]
Block Transfer Count [7:0]
Clk Out of
R/W
R/W
Sync
3
Description
none
del05 x 1
del05 x 2
del05 x 3
(page
2
4-47).
Reserved
1
R/W [5:4]
PLL Test
R/W 0
0
0
[2:1]
4-43
R 3