L64105 LSI Logic Corporation, L64105 Datasheet - Page 190

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.4.2 Host DMA SDRAM Transfers
5-14
Host DMA transfers to/from SDRAM through the L64105 are supported
with the DMA Transfer Request (DREQn) output signal. This signal is
asserted to the host during DMA reads when the DMA RdFIFO contains
more than one 64-bit word and during DMA writes when the DMA
WrFIFO has space left for more than one 64-bit word. Control of the
DREQn signal is determined by the setting of the DMA Mode bits in
Register 193 as shown in
Table 5.3
The DREQn signal can be used as an input to a host DMA controller that
accepts a level-sensitive DREQn input. The DMA controller can read a
few bytes beyond the end timing of the DREQn pin and still function
correctly. Note that the DREQn signal will continue to request data
transfer for a read or write operation after the DMA controller has
reached the terminal count. The L64105 is not responsible for monitoring
the DMA terminal count.
Host DMA read/write operations may proceed in parallel with standard
host read/write operations. The registers, FIFOs, and counters for DMA
and host operations are completely independent. Since there is only one
physical data access port on the L64105, the host must arbitrate host
read/write and DMA read/write operations through it.
Block move operations may NOT proceed in parallel with host read/write
operations or DMA read/write operations. The block move corrupts any
data left in the FIFOs at the time the block move begins.
Host Interface
Register 193[2:1]
0b00
0b01
0b10
0b11
DMA Mode Bits
DMA Mode
DMA Idle; DREQn = 1
DMA Read; DREQn = RdFIFO near-empty
DMA Write; DREQn = WrFIFO near-full
Block Move; DREQn = 1
Table
5.3.