L64105 LSI Logic Corporation, L64105 Datasheet - Page 140

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.86
4.5 Video Interface Registers
Figure 4.87
4-58
Force Video Background
7
7
[1:0]
Register 248 (0x0F8) Reduced Memory Mode (RMM) Bit
Register 265 (0x109)
6
Register 247 (0x0F7)
When set, this bit enables the Reduced Memory Mode (RMM) required
for PAL resolution (720 x 576). This mode has the capability to use less
than one frame store SDRAM memory space for B pictures provided
some restrictions are met. These restrictions include no “repeat-first-
field” for B pictures.
RMM is achieved by dynamically allocating segments of memory to the
reconstruction and display processes. Re-use of segments is possible in
the case of B pictures, thus reducing the frame store memory
requirement for B pictures. When this bit is cleared, the chip is in regular
memory mode.
Registers 249–255 (0x0F9–0x0FF) Reserved
Registers 256–264 (0x100–0x108) Reserved
OSD Mode [1:0]
Register Descriptions
Display Override Mode [1:0]
5
The On-Screen Display (OSD) Mode field determines the
source of OSD data, either internal or external, per the
following table.
Mode Bits
0b00
0b01
0b10
0b11
Reserved
4
Reserved
Palette Counter
Clear OSD
Description
No OSD (Disabled)
Internal OSD (Contiguous)
Internal OSD (Linked List)
External OSD
3
Reserved
2
1
OSD Mode [1:0]
1
Mode (RMM)
R/W [1:0]
Reduced
Memory
R/W
0
0
[7:0]
[7:0]
[7:0]