L64105 LSI Logic Corporation, L64105 Datasheet - Page 38

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2.5 Video Interface
2-8
SWEn
SCLK
Important:
PD[7:0]
CREF
BLANK
OSD_ACTIVE
EXT_OSD[3:0]
I/O Signal Descriptions
SCLK should be connected through a 33-
resistor mounted as close as possible to the SCLK pin of
the L64105.
SDRAM Write Enable
The Memory Interface asserts SWEn for SDRAM write
cycles and holds it deasserted for SDRAM read cycles.
SDRAM 81-MHz Clock
The 27-MHz SYSCLK input is multiplied by three using
the on-chip PLL to generate the 81-MHz SCLK.
Pixel Data Output Bus
The PD[7:0] bus carries the pixel data for the
reconstructed pictures. The pixel data is formatted in
ITU_R BT.601 Y, Cb, Cr chromaticity.
Chroma Reference
The Video Interface asserts CREF when the Cb
component of Chroma is on PD[7:0] and deasserts it at
all other times.
Blank
BLANK is a composite blank output from the L64105
display controller. Its polarity is user-defined.
On-Screen Display
The Memory Interface asserts this signal to indicate that
the on-chip OSD pixel on PD[7:0] is nontransparent. This
signal indicates which pixels have mixed OSD.
Palette Selection Bus
The host controls an external device (such as a character
generator) to write half-bytes across this bus to select
colors from a 16-color look-up table in the L64105 to be
used for external OSD.
terminating
Output
Output
Output
Output
Output
Output
Input