L64105 LSI Logic Corporation, L64105 Datasheet - Page 364

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

10.9.3 IEC958 Channel Status
Figure 10.15 IEC958 Channel Status
10.10 Clock Divider
10-32
Byte 0
Byte 1
Byte 2
Byte 3
Mode Only
Consumer
0 for
0
Sampling Frequency (44.1/48/32)
Source Number = 0b0000
1 = Formatter
0 = Decoder
The L64105 uses the first 32 C bits of each channel in each block to
carry the four bytes of channel status information shown in
The remaining C bits in the blocks are cleared to 0. The Copyright and
Emphasis bits are from the incoming bitstream. The S/P DIF Interface
inserts one of the two Category Codes shown in the following table:
The host can overwrite the Copyright bit, the Emphasis bits, and
Category Code by setting the associated overwrite bit in Registers 355
(page
Category field in Register 367. The remaining bits and fields of the
channel status bytes are fixed or filled in by the S/P DIF Interface as
shown in
As mentioned in the output interface descriptions, the Clock Divider in
the Audio Decoder derives a BCLK for each interface and an LRCLK and
A_ACLK for the external DACs from an input audio clock. The L64105
has three audio clock input pins, ACLK_32, ACLK_441, and ACLK_48 for
Audio Decoder Module
Output,
Data Format
PCM Samples
Digital Data
Output
1
4-87) and 366, and writing to the Emphasis bit, Copyright field, or
Figure
Copyright
2
Category Code (User Programmable)
10.15.
Default Category Code
0b0000.0000
0b1001.1000
3
Emphasis from Bitstream
Clock Accuracy = 0b01
4
Channel (L = 0b1000, R = 0b0100,
Don’t Care = 0b0000)
5
6
Mode = 0b00
Figure
10.15.
7