L64105 LSI Logic Corporation, L64105 Datasheet - Page 88

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

4-6
Audio PES Data Ready Interrupt
Video PES Data Ready Interrupt
Reserved
Seq End Code in Video Channel Interrupt
Reserved
DTS Audio Interrupt
DTS Video Event Interrupt
Register Descriptions
This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects an audio PES packet. This
bit is cleared when read. INTRn is not asserted if the host
sets the mask bit.
This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects a video PES packet. This
bit is cleared when read. INTRn is not asserted if the host
sets the mask bit.
Set this bit when writing to this register.
This bit is set and INTRn is asserted (if not masked) by
the preparser when it detects a sequence end code in the
video channel. This bit is cleared when read. INTRn is
not asserted if the host sets the mask bit.
Set this bit when writing to this register.
When the chip is in the Audio Read Compare mode
(Register 69, bits 1 and 2,
controller generates a single cycle pulse when the read
pointer in the channel buffer matches a preset value
(Registers 111, 112, and 113,
an internal state machine waits for an audio sync code,
sets this bit, and then generates an interrupt by asserting
the INTRn output signal. The interrupt is used for
audio/video synchronization.
This bit is cleared when read. INTRn is not asserted if the
host sets the mask bit.
When the chip is in the Video Read Compare mode
(Register 69, bit 0,
controller generates a single cycle pulse when the read
pointer in the channel buffer matches to a preset value
(Registers 108, 109, and 110,
an internal state machine waits for a picture start code,
sets this bit, and then generates an interrupt by asserting
page
4-21), the channel buffer
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page
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4-21), the channel buffer
4-28). At the pulse,
4-28). At the pulse,
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