L64105 LSI Logic Corporation, L64105 Datasheet - Page 209

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 6.6
Elementary
Elementary
The start and end addresses of each of the buffers are programmed by
the host in the registers listed in
Table 6.8
These registers hold the upper 14 bits of the buffer addresses. The
SDRAM Controller programs the address bits so that the addresses are
on 256-byte boundaries. The host can write to these registers only when
the channel is stopped.
The buffers are maintained as circular FIFOs. The current read and write
pointers for each of the buffers are written to registers (listed in
and available to the host. Actually, only the LSB registers are continually
updated. When the host reads the LSB, the next byte and the MSB
registers are then updated. Also, the number of items in each channel is
provided in host registers:
Preparser
Addresses
Video ES Channel Buffer Start Address
Video ES Channel Buffer End Address
Audio ES Channel Buffer Start Address
Audio ES Channel Buffer End Address
VVALIDn
AVALIDn
AREQn
VREQn
Stream
Stream
Audio
Video
Elementary Stream Buffering
Buffer Start and End Address Registers for ES Mode
Preparser and
Write FIFO
L64105
Table
6.8.
Audio ES
Video ES
SDRAM
Channel
Channel
Registers
72 and 73
74 and 75
76 and 77
78 and 79
Buffer
Buffer
Page Ref.
Table
4-22
4-23
4-23
4-24
6.9)
6-13