L64105 LSI Logic Corporation, L64105 Datasheet - Page 191

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.4.2.1 DMA Read
The system can use a dual-address DMA controller with a
nonincrementing source address for DMA read operations. For a DMA
read (refer to
prevent DMA operation until everything is ready. This holds DREQn to
the host deasserted. Next, the host sets the DMA Transfer Byte Ordering
bit to the DMA controller’s endian, if necessary. Then the host writes the
SDRAM starting address of the transfer to the DMA SDRAM Source
Address registers. When the LSB of the source address is written into its
register, the L64105 flushes the DMA RdFIFO and starts refilling it from
the source address. To start the read, the host sets the DMA Mode bits
to Read. Since there should be more than one 8-byte word in the
RdFIFO at this time, DREQn is asserted to the host.
The external DMA controller then starts reading the data bytes from the
DMA SDRAM Read Data register. DREQn will remain asserted so long
as there are at least two words in the RdFIFO. The L64105 SDRAM
controller automatically increments the source address after each 8-byte
word is read from the SDRAM into the DMA RdFIFO.
The external DMA controller is responsible for setting the initial transfer
count and decrementing it after reading each 8-byte word. The SDRAM
controller will continue to increment the SDRAM address and transfer
bytes into the DMA RdFIFO until the FIFO is full or the host changes the
DMA Mode. In a normal DMA read, the DMA controller must stop reading
bytes from the DMA SDRAM Read Data register when its transfer count
reaches zero even though DREQn is still asserted. The L64105 SDRAM
controller fills the RdFIFO if it is not already full. After the transfer count
reaches zero, the host must read the DMA Read FIFO Full bit. When the
hosts detects that the full bit is set, it should set the DMA Mode to Idle
to deassert DREQn.
SDRAM Access
Note:
The L64105 requires one clock cycle after the DMA
RdFIFO is full to set the DMA RdFIFO Full bit. The host
should wait for one clock cycle before reading the bit.
Figure
5.9), the host first sets the DMA Mode to Idle to
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