L64105 LSI Logic Corporation, L64105 Datasheet - Page 237

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

7.6 Memory Frame Store Allocation
7.6.1 Luma Store
Figure 7.5
Word 89
Word 90
7.6.2 Chroma Store
Word 0
Word 1
0
Y712
Y0
Y8
Y0
Luma Frame Store Organization
Y713
Y1
Y9
Y1
The SDRAM space allocated for video frame stores is dependent upon
the operating mode of the device and the largest picture size expected
in the bitstream. The size of the frame store cannot be altered while the
video decoder is running. These values must be programmed at power-
up time or at the channel-start time when the sequence header arrives.
The pixel data in the frame store is arranged in a Luma (L) frame store
and a Chroma (C) frame store.
If the reconstructed image is 720 pixels wide, then each line of luminance
occupies 720 bytes. Since there are 8 pixels in a 64-bit word, one line of
luminance requires 90 64-bit words or 90 bursts to SDRAM. Each frame
store starts with the upper left pixel in the reconstruction space and
increments in address as the frame store progresses across the pixel
line. At the end of a reconstruction line, the next line starts immediately
at the next 64-bit word address.
The chroma data is stored slightly differently. The L64105 interleaves
chroma pixels (Cr, Cb, Cr, Cb) within the same 64-bit word to increase
the word fetch efficiency of the SDRAM interface. Each CrCb pair is
stored in consecutive bytes in the 64-bit word. There is one CrCb pair for
every two pixels. This results in a frame store with the same number of
addresses per line in chroma as in luma. However, there are half the
Memory Frame Store Allocation
Y714
Y10
Y2
Y2
Y715
Y11
Y3
Y3
Y716
Y12
Y4
Y4
Y717
Y13
Y5
Y5
Y718
Y14
Y6
Y6
Y719
Y15
Y7
Y7
63
Frame Start Address
7-9