L64105 LSI Logic Corporation, L64105 Datasheet - Page 84

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

4.1 Host Interface Registers
Figure 4.1
4-2
Read
Write
New Field
New Field
Interrupt
Mask
7
Register 0 (0x000)
Audio Sync
Audio Sync
Recovery
Recovery
Interrupt
Decode Status Interrupt
Aux/User Data FIFO Ready Interrupt
Register Descriptions
Mask
6
Reserved
Reserved
5
This bit is set when the video decode status changes
from stopped to running (0 to 1) and cleared when the
status changes from running to stopped (1 to 0). Either
status change causes assertion of the INTRn interrupt
signal to the host if not masked. The 0 to 1 transition
occurs on a picture start code boundary after channel
start. It is linked in timing to the last field of the display
system. The decode status is updated internally and may
change when one of the following events is recognized by
the internal microcontroller:
1. A write to the Decode Start/Stop Command register
(page
2. When the Video Start on Compare register
is set by the host and a compare occurs. In this case, the
status goes from stopped to running.
Reading this register does NOT change the Decode
Status bit.
INTRn is not asserted if the host sets the mask bit.
When set, indicates there is new data in the Aux or User
Data FIFO ready to be read. A NOT ready (0) to ready
(1) change causes assertion of the INTRn signal if not
masked. The status of the Aux Data FIFO
and User Data FIFO
determine which has valid data. The bit is cleared on
reading. Even though data remains in the FIFOs, no
further interrupts are generated.
INTRn is not asserted if the host sets the mask bit.
Done Mask
Interrupt
SDRAM
SDRAM
Transfer
Transfer
4-57) by the host.
Done
4
Detect Mask
Sequence
End Code
Sequence
End Code
Interrupt
Detect
3
(page
Detect Mask
Start Code
Start Code
First Slice
First Slice
Interrupt
Detect
4-18) can be read to
2
Ready Mask
Data FIFO
Data FIFO
Aux/User
Aux/User
Interrupt
Ready
1
(page
(page
Status Mask
Interrupt
Decode
Decode
Status
4-17)
4-16)
0
0
1