L64105 LSI Logic Corporation, L64105 Datasheet - Page 201

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

6.2.2 Synchronous VALIDn Inputs
3. The system must respect the function of the AREQn/VREQn signals.
4. The DCK pin of the decoder must be tied to V
When the DCK input is connected, the L64105 uses it to internally
synchronize the input VALIDn signals before they strobe data in. This
mode is recommended for connecting devices that do not have clean
AVALIDn/VVALIDn signals.
The synchronizing circuits in the L64105 are shown in
DCK is not connected in from the upstream device, AVALIDn and
VVALIDn strobe audio and video bytes in from the CH_DATA[7:0] bus on
their rising edges. When DCK is supplied, it is gated through when either
VALIDn signal is asserted. The gated rising edges of DCK then strobe
data in. When the Invert Channel Clock bit is set, DCK is inverted
through the exclusive OR before being gated by the VALIDn signals. The
timing for synchronous valid signals is shown in
Interface Signals Operation
The timing restriction above will allow enough space within the input
channel FIFO to allow an external synchronizer on the
AREQn/VREQn signals. This allows writing data beyond
AREQn/VREQn rising edge by 1 byte.
Channel Clock bit in Register 5
(page
4-9) must be cleared.
Figure
SS
, and the Invert
Figure
6.4.
6.3. When
6-5