L64105 LSI Logic Corporation, L64105 Datasheet - Page 178

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.1
5.2 Interface Signals
5-2
Host
Interrupt
Transfer
Control
Ready,
D[7:0]
A[8:0]
Host Interface Block Diagram
L64105
Host Interface
Registers
The host interface is configurable for either an Intel or a Motorola
processor.
configuration selection is made by tying the BUSMODE pin of the chip
to a VDD (+ 3.3 V) or a VSS (ground) pin.
Table 5.1
Host Interface
8-bit
Signal
BUSMODE
A[8:0]
ASn
D[7:0]
DSn/WRITEn
CSn
512
Big/Little Endian
Control, Status,
and Interrupts
Buffer Start and
End Addresses,
Read/Write Pointers
Enable
Logic
Table 5.1
Byte
Host Interface Signals
L64105 Direction
Input
Input
Input
Input/Output
Input
Input
Read
Write
FIFO
FIFO
lists the signals for each processor. The
Modules
To/From
Internal
Other
64-bit
Bus
Intel Mode
Tied low (logic 0). Tied high (logic 1).
A[8:0]
ASn
D[7:0]
WRITEn
CSn
Interface
Memory
SCSn
SCASn
SRASn
A[11:0]
D[15:0]
SCS1n
Motorola Mode
A[8:0]
ASn
D[7:0]
DSn
CSn
(Optional)
1 M x 16
1 M x 16
SDRAM
SDRAM