L64105 LSI Logic Corporation, L64105 Datasheet - Page 165

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.123 Register 359 (0x167) PCM FIFO Data In [7:0]
Figure 4.124 Register 360 (0x168) Linear PCM - dynscalehigh [7:0]
Figure 4.125 Register 361 (0x169) Linear PCM - dynscalelow [7:0]
7
7
7
The host should issue four consecutive write operations for each pair of
PCM samples to be played at the output when the PCM FIFO Mode is
enabled (see Audio Decoder Mode Select [2:0] on
data should be written to this register in the following order: Left Channel
LSB, Left Channel MSB, Right Channel LSB, and Right Channel MSB.
This register is write only.
This is an 8-bit, fractional, scale factor for scaling the dynrng value coded
in the bitstream. The dynscalehigh factor is applied when the dynrng
value in the bitstream indicates a negative dB gain. dynscalehigh = 0x00
disables the dynrng scaling intended in the bitstream;
dynscalehigh = 0xFF applies the full dynamic range scaling coded in the
bitstream. Intermediate values (dynscalehigh = 0x01, ..., 0xFE) scale the
dynrng value by factors of 2/256 to 255/256. The dynscalehigh setting
can be used to effectively boost the dynamic range of the program. The
default value of this register is 0xFF.
This is an 8-bit, fractional, scale factor for scaling the dynrng value coded
in bitstream when it is a positive dB gain. See dynscalehigh in the
previous register.
Audio Decoder Registers
Linear PCM - dynscalehigh [7:0]
Linear PCM - dynscalelow [7:0]
PCM FIFO Data In [7:0]
R/W
R/W
W
page
4-81). The PCM
0
0
0
4-83