L64105 LSI Logic Corporation, L64105 Datasheet - Page 173

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.133 Registers 369 and 370 (0x171 and 0x172) Host Pd Value [15:0]
4.7 RAM Test Registers
Figure 4.134 Registers 384 and 385 (0x180 and 0x181) Memory Test Address [11:0]
Figure 4.135 Register 386 (0x182)
Reg. 369
Reg. 370
Reg. 384
Reg. 385
MSB
MSB
LSB
LSB
7
Reserved
7
7
6
When the Pd Selection bits (3 and 4 in Register 368) are 0b10 (host
force mode), the host must write a Host Pd Value for the Pd field in the
preamble of the MPEG audio burst into these registers. The Pd field
should contain the length of the burst payload in bits. See
page 10-21
Registers 371–383 (0x173–0x17F) Reserved
The host writes an address to these registers for a host-controlled testing
of a single address (bits [1:0] of Register 386 set to 0b01). During
automated test modes, these registers are updated by the L64105 to
indicate the progress of the tests.
Operational Mode for RAM Test [1:0]
RAM Test Registers
Output Select
Memory Test
Reserved
5
to determine the Pd value.
The host writes to this field to specify the type of memory
test to be run according to the following table.
Data Pattern to be Applied
4
Memory Test Address [7:0]
to RAM [1:0]
Host Pd Value [15:8]
Host Pd Value [7:0]
4
R/W
R/W
R/W
3
3
Report End of
Memory Test
Test/Initiate
Memory Test Address [11:8]
2
R/W
Operational Mode for RAM
1
Test [1:0]
Table 10.5
W [1:0]
0
0
0
[7:0]
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on