L64105 LSI Logic Corporation, L64105 Datasheet - Page 109

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.33
Figure 4.34
Reg. 102
Reg. 103
Reg. 104
Reg. 108
Reg. 109
Reg. 110
MSB
MSB
LSB
LSB
Registers 102–104 (0x066–0x068) Video PES Header Channel Buffer
Write Address [19:0]
Registers 108–110 (0x06C–0x06E) Video ES Channel Buffer Read
Address [19:0]
7
7
These registers contain the current write pointer address of the Video
PES Header channel buffer. The LSB should be read first. since this
captures the next significant byte and MSB in Registers 103 and 104.
These should then be read immediately to ensure that the correct
captured value is read. When set, the most significant bit (bit 3 of
Register 104) indicates that the write pointer has wrapped around from
the end address to the start address of the buffer.
Registers 105–107 (0x069–0x06B) Reserved
These registers contain the current read pointer address of the Video ES
channel buffer. The LSB should be read first since this captures the next
significant byte and MSB in Registers 109 and 110. These should then
be read immediately to ensure that the correct captured value is read.
When set, the most significant bit (bit 3 of Register 110) indicates that
the read pointer has wrapped around from the end address to the start
address of the buffer.
Video Decoder Registers
Reserved
Reserved
Video PES Header Channel Buffer Write Address [15:8]
Video PES Header Channel Buffer Write Address [7:0]
Video ES Channel Buffer Read Address [15:8]
Video ES Channel Buffer Read Address [7:0]
4
4
Read Only
Read Only
Read Only
Read Only
Video ES Channel Buffer Read Address [19:16]
3
3
Video PES Header Channel Buffer
Write Address [19:16]
Read Only
Read Only
0
0
[7:0]
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