L64105 LSI Logic Corporation, L64105 Datasheet - Page 332

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 9.20 Video and Control Output Timing
PXL DATA
9.14 Display Controller Interrupts
9-40
SYSCLK
BLANK
CREF
0x10
The Display Controller sets two interrupt bits in response to field timing,
the Begin Active Video Interrupt bit and Begin Vertical Blank Interrupt bit,
both in Register 1
asserted to the host when either bit is set. The time at which these
interrupts occur within each field time is based upon how the active
display area is programmed by the host.
The host controls the location of the active display area by programming
the SAV/EAV code parameters. Regardless of whether the target system
requires the SAV/EAV tokens in the video stream, the SAV/EAV
parameters must be programmed for proper operation of the Display
Controller.
The Begin Active Video Interrupt occurs during the EAV when there is a
transition in the Vcode from 1 to 0. The host processor controls this
transition by programming the Vcode Zero bits in Register 303
(page
The Begin Vertical Blank Interrupt occurs during the EAV when the
Vcode transitions from 0 to 1. The host controls this transition by
programming the Vcode Even bits in Registers 303 and 304.
Video Interface
FF
4-70).
00
00
(page
4-4). If the bits are not masked, INTRn is
XY
Cb0
Y0
Cr0
Y1