L64105 LSI Logic Corporation, L64105 Datasheet - Page 42

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

2-12
SYSCLK
TM[1:0]
ZTEST
SCAN_TE
I/O Signal Descriptions
Device Clock
Device clock has a nominal frequency of 27 MHz. Picture
reconstruction and video timing are referenced with
respect to this clock. SYSCLK also drives the PLL to
generate the 81-MHz clock for the SDRAM interface.
Test Mode
These inputs are used by LSI Logic during manufacturing
test. They are not exercised in a customer system. They
should both be tied to VSS in the system.
Test Mode
Test mode pin. This should be tied to VDD in the system
for normal operation. Forcing this signal LOW 3-states all
outputs allowing for simple PCB bed-of-nails testing.
Test Mode
Test mode pin. This should be tied to VSS in the system
for normal operation.
Input
Input
Input
Input