L64105 LSI Logic Corporation, L64105 Datasheet - Page 180

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.3
5-4
DTACKn
READ
D[7:0]
A[8:0]
CSn
DSn
ASn
Motorola Mode Read Timing
The cycle can be terminated by the L64105 setting DTACKn high or by
the host deasserting CSn. When CSn is deasserted, the L64105 3-states
its DTACKn output.
The Motorola mode read timing is shown in
is very similar to that for write. The only difference is that the READ
signal is asserted for the cycle.
The write and read timing for Intel host processors is shown in
and
address is strobed onto A[8:0] at the negative-going edge of the
read/write signal, and the data is strobed into the L64105 on the positive-
going edge of the read/write signal. The address can be placed on the
bus even though the L64105 is not ready for the transfer. The host holds
the WRITEn signal asserted until the L64105 asserts DTACKn. If the
decoder does not respond within 107.5 ns of the falling edge of WRITEn,
the host aborts the write. For a read, the host waits for 144.5 ns from the
falling edge of READn for DTACKn to be asserted before aborting the
operation.
Host Interface
Figure
5.5. Intel processors use separate read/write signals. The
Figure
5.3. The read timing
Figure 5.4