L64105 LSI Logic Corporation, L64105 Datasheet - Page 194

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

5.4.2.3 DMA Bandwidth
5.4.3 SDRAM Block Move
5-18
During DMA, the L64105 can support a bandwidth of a sustained rate of
approximately 2.5 Mbytes/sec. During the transfer of data, the rate can
increase for short periods of time.
The SDRAM block move, flowcharted in
specify a block of data to be copied from one SDRAM location to another
SDRAM location.
Important:
To perform a block move, the host first sets the DMA Mode to Idle. Then
it writes the number of contiguous 64-bit words to be moved into the
Block Transfer Count registers. The host writes the move from address
into the DMA SDRAM Source Address registers and the move to
address into the DMA SDRAM Target Address registers. To start the
move, the host sets the DMA Mode to Block Move.
The L64105 SDRAM controller performs the block move and sets the
SDRAM Transfer Done Interrupt bit at the completion. If the SDRAM
Transfer Done Interrupt is not masked by the host, the L64105 also
asserts the INTRn signal to the host to notify it of the move completion.
The L64105 automatically sets the DMA Mode to Idle at the move
completion.
Host Interface
Some care should be taken when executing an SDRAM
block move. The SDRAM block move should not be
performed in parallel with any other SDRAM transfer; host
read, host write, DMA read, or DMA write. All SDRAM
transfers should be completed before a block move is
started. The block move should be completed before any
other SDRAM transfer is attempted.
Block moves cannot be executed on data blocks smaller
than one 64-bit SDRAM word.
It is the host’s responsibility to ensure that the transfer
count agrees with the difference between the start and end
addresses.
Figure
5.10, allows the host to