L64105 LSI Logic Corporation, L64105 Datasheet - Page 266

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

8.3 Video Decoder Pacing
8-24
Table 8.17
When the host writes a 1 to bit 0 of Register 65, the read and write
pointers of the User Data FIFO are reset and the FIFO’s status goes to
empty. Any previously unread bytes in the FIFO will be overwritten and
lost when new data is written into the FIFO.
When the GOP User Data Only bit is set, the decoder parses only user
data at the GOP layer (line 21) to the User Data FIFO. Other user data
is discarded by the decoder. The default value of this bit at startup is 0;
all user data of all layers are written to the User Data FIFO.
The Video Decoder Module in the L64105 decodes preparsed data from
the Video ES Channel Buffer. Decode should not be started until there
is sufficient data in the Video ES Channel Buffer to decode a complete
picture without the buffer underflowing. To decode with the minimum
amount of frame store memory, picture reconstruction is controlled by the
picture display rate (i.e., the vertical sync rate). The decode-to-display
pacing is actually performed by comparing the Decode Time Stamp
(DTS) and Presentation Time Stamp (PTS) of each picture to the System
Clock Reference (SCR). The Video Decoder Module is controlled by the
Decode Start/Stop Command bit (Register 246, bit 0). Setting this bit
causes the decoder to start the process of reconstructing pictures from
the input MPEG-1/MPEG-2 bitstream. The reconstruction proceeds in
lock step with the display. This is required to decode with the minimum
allowable amount of frame store memory. The rate of reconstruction is
therefore controlled by the rate at which the picture is displayed, which
again is controlled by the external sync signals (HS and VS signals).
Video Decoder Module
User Data Layer ID [1:0]
0b00
0b01
0b10
0b11
User Data Layer ID Assignments
MPEG Layer
sequence
Group of pictures
Picture
Slice