L64105 LSI Logic Corporation, L64105 Datasheet - Page 297

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

9.3 Display Areas
Table 9.2
From the Display Controller point of view, the entire display area can best
be described as a blank area that is bounded vertically by the vertical
sync (VS) input and horizontally by the horizontal sync (HS) input. The
HS and VS input pulses determine field and line timing. For reliable
operation, the sync inputs must be synchronous to the 27-MHz device
clock. Additionally, VS must be received every field time and HS must be
received every line time.
The Display Controller times and locates several display areas within the
entire display area. Refer to
display area, the main display area, and the OSD area. The bottom-most
layer is black. The active display area resides just above the black layer.
The main display area is contained within the active display area. The
OSD display is mixed on top of the main area.
Display Areas
Parameter
Main Reads Per Line[6:0]
Vline Count Init[2:0]
Pixel State Reset Value [1:0] 284[4:3]
Main Start Row[10:0]
Main End Row[10:0]
Main Start Column[10:0]
Main End Column[10:0]
SAV Start Col[10:0]
EAV Start Co[10:0]l
Vcode Zero[4:0]
Vcode Even[8:0]
Vcode Even Plus 1
Fcode[8:0]
Television Standard Select Default Values
Register[Bits]
278[6:0]
282[2:0]
299[2:0], 297[7:0]
299[6:4], 298[7:0]
302[2:0], 300[7:0]
302[6:4], 301[7:0]
308[2:0], 306[7:0]
308[6:4], 307[7:0]
303[4:0]
303 bit 5, 304[7:0]
303 bit 6
303 bit 8, 305[7:0]
Figure
9.2. The areas include the active
NTSC
1683
1684
262
244
240
262
265
90
23
21
4
2
1
1703
1704
PAL
310
264
260
310
312
90
23
21
1
2
0
Page Ref.
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4-70
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4-70
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