L64105 LSI Logic Corporation, L64105 Datasheet - Page 232

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 7.1
Figure 7.2
7-4
DQ[15:0]
Parameter
Time (ns)
No. of Cycles
81 MHz
SRASn
SCASn
A[10:0]
SWEn
SCSn
NEC’s 16 Mbit Synchronous DRAM (Burst Length = 2)
SDRAM Timing Requirements for Reads
act0
row
0
0
act0 - act1
T
T
RCD
refresh modes. For exact timing, refer to the SDRAM vendor’s data
sheet.
Memory Interface
RRD
36
3
read0
col row
CAS Latency
act1
1
1
act - r/w
T
T
RCD
29
3
RAS
0
read1
col
1
0
pre0
0
0
0
0
pre - act
T
0
36
3
RP
1
act0
row
1
pre1
act - pre
1
1
T
RAS
84
7
1
T
read0
RP
col row
0
act1
1
1
ref - ref/act
T
120
10
RC
read1
0
col
1
1
0
pre0
0
0
0
0
0
CAS Latency
1
–
3