L64105 LSI Logic Corporation, L64105 Datasheet - Page 120

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.52
4.3 Memory Interface Registers
Figure 4.53
4-38
Reg. 150
Reg. 151
DMA Write
FIFO Full
MSB
LSB
7
FIFO Empty
DMA Write
Registers 150 and 151 (0x096 and 0x097) Pictures in Video ES Channel
Buffer Counter [15:0]
Register 192 (0x0C0)
7
6
Reserved
These registers allow the host to read the number of pictures currently
in the Video ES channel buffer.
Registers 152–191 (0x098–0x0BF)
These read-only bits contain the empty/full status of the four, 8 x 64-bit,
internal FIFOs used during host/SDRAM read or write operations. The
host should read this register before transfers to avoid reading from an
empty FIFO or writing to a full FIFO. Refer to
Access,”
empty bits are set and the FIFO full bits are cleared at reset.
Register Descriptions
DMA Read
FIFO Full
5
for more details on host/SDRAM transfer operations. The FIFO
Pictures in Video ES Channel Buffer Counter [15:8]
Pictures in Video ES Channel Buffer Counter [7:0]
FIFO Empty
DMA Read
4
Read Only
Read Only
Host Write
FIFO Full
3
FIFO Empty
Reserved
Host Write
2
Section 5.4, “SDRAM
Host Read
FIFO Full
1
FIFO Empty
Host Read
0
0
[7:2]
[7:0]