L64105 LSI Logic Corporation, L64105 Datasheet - Page 288
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L64105
Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
1.L64105.pdf
(454 pages)
- Current page: 288 of 454
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Figure 8.9
Rip Forward Single Step
Rip Forward Mode Enable
Display Override Enable
Display
Force Rate Control On
Automatic Rate Control On
Note:
8.5.8 Sequence End Processing
8-46
Names inside parentheses indicate frame store being used for decode or display.
F = First field.
L = Last field.
P1(A2)
Using Force Rate Control in Rip Forward Mode
I0(A1)
F
When the Video Decoder detects a sequence end code in the bitstream,
it sets the Sequence End Code Detect Interrupt bit in Register 0
(page
bit is not masked. After a sequence end code, the Video Decoder
displays any decoded but undisplayed anchor pictures (I or P) and
freezes the last frame on the display until the next sequence start code
is detected. This may be valuable information to the host software in
certain situations, such as displaying still images.
With the 3-frame store scheme, an anchor picture should not be
displayed until the next anchor picture is encountered. This causes at
least a 3-field display delay between an anchor picture’s reconstruction
and its display. Case 1 in
right after a sequence end code. At the sequence end code, frame P2 is
already decoded and waiting to be displayed. The Video Decoder
displays it.
Video Decoder Module
P2(A1)
L
4-3) and this asserts the INTRn signal to the host if the interrupt
P2(A1)
P3(A2)
F
P4(A1)
L
P4(A1)
Figure 8.10
P5(A2) P6(A1)
Host set rip forward single step
F
Rip forward single step cleared by decoder
L
shows a new sequence starting
P5(A2)
F
P7(A2)
L
P6(A1)
F
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