L64105 LSI Logic Corporation, L64105 Datasheet - Page 124

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.57
Figure 4.58
4-42
Reg. 196
Reg. 197
Reg. 198
Reg. 199
Reg. 200
Reg. 201
MSB
MSB
LSB
LSB
Registers 196–198 (0x0C4–0x0C6) Host SDRAM Target Address [18:0]
Registers 199–201 (0x0C7–0x0C9) Host SDRAM Source Address [18:0]
7
7
For a host write to SDRAM, the host must write the starting SDRAM
address in this register. This address is automatically incremented after
eight bytes are transferred to SDRAM through Register 195 and the
internal, 8 x 64, write FIFO. The host should update the SDRAM target
address only when the write FIFO is empty.
For a host read from SDRAM, the host must write the starting SDRAM
address in this register. This address is automatically incremented after
eight bytes are transferred to the internal, 8 x 64, read FIFO. The host
should update the SDRAM source address only when the read FIFO is
full, allowing a clean flush of the read FIFO. When updating the SDRAM
source address, the LSB of the address should be written last. This
triggers the refill of the read FIFO at the new address.
Register Descriptions
Reserved
Reserved
Host SDRAM Source Address [15:8]
Host SDRAM Target Address [15:8]
Host SDRAM Source Address [7:0]
Host SDRAM Target Address [7:0]
R/W
R/W
R/W
R/W
3
3
Host SDRAM Source Address [18:16]
Host SDRAM Target Address [18:16]
2
2
R/W
R/W
0
0