L64105 LSI Logic Corporation, L64105 Datasheet - Page 98

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.14
Figure 4.15
4-16
Reg. 20
Reg. 21
Reg. 22
Reg. 23
MSB
LSB
7
Registers 20–23 (0x014–0x017) SCR Compare Audio [31:0]
Register 28 (0x01C) Video Channel Bypass Data [7:0]
7
Video Start on Compare
Reserved
When the Audio Start on Compare bit in Register 19
the SCR Compare/Capture mode is Compare, and the SCR Counter
reaches the value in these registers, an autostart pulse is generated to
start the Audio Decoder.
The compare also sets the SCR Compare Audio Interrupt bit (bit 2 in
Register 1,
masked. The Audio Start on Compare bit is cleared when the compare
event occurs.
Registers 24–27 (0x018–0x01B) Reserved
Register Descriptions
page
Video Channel Bypass Data [7:0]
register. This autostart pulse also clears the Audio Start
on Compare bit. The Audio Decoder must be in Pause
Mode for the autostart signal to be effective.
When the L64105 is in the Compare Mode, setting this
bit generates a single-cycle, autostart pulse to start the
Video Decoder when current value of the SCR Counter
is equal to the value in the SCR Compare register. This
bit is cleared after the autostart signal is generated.
4-4) and asserts the INTRn signal to the host if not
SCR Compare Audio [23:16]
SCR Compare Audio [31:24]
SCR Compare Audio [15:8]
SCR Compare Audio [7:0]
W
R/W
R/W
R/W
R/W
(Figure
4.13) is set,
R/W 1
0
0
[7:2]
[7:0]