L64105 LSI Logic Corporation, L64105 Datasheet - Page 433

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

L64105 data rates
L64105 horizontal resolution
L64105 I/O signals block diagram
large images
last field bit
latency
layers
letterbox display mode 9-18,
letterbox filtering
letterboxing 1-4, 8-33,
line offset 4-66,
linear PCM - dynscalehigh bits
linear PCM - dynscalelow bits
linear PCM decoder 1-4, 10-14,
linear PCM dynamic range on bit
linear PCM stream select
linked list
little endian byte ordering 4-40,
LPCM
LRCLK bit inversion
LRCLK signal
PCB layout connections
resetting
specifications
external OSD
full resolution images
luma/chroma filtering 9-18,
SIF images
audio channel buffers
audio samples 10-3,
audio samples syntax
audio stream errors
bitstream parameters 4-77,
dynamic range enable 4-87,
fast playback rate 4-79,
features
FIFO status bits
mode selection bit
output ports
sample conversion
sample output requests
sample overwrite category
sample writes 4-83,
scaling factor 4-83, 4-84,
serial data out timing
slow playback rate 4-79,
start/stop bit
stream permutations
OSD formats
description
usage overview 10-29,
A-8
PCM FIFO mode
sampling frequency
B-5
7-3
9-26
10-2
4-63
4-12
9-19
2-10
2-10
9-16
10-19
9-6
4-80
9-29
7-11
11-1
9-32
A-1
4-77
4-84
4-81
9-4
4-81
6-24
10-6
10-16
10-26
10-15
Index
11-17
9-16
6-20
10-16
4-34
10-18
10-32
2-5
10-7
2-7
10-7
A-1
10-17
9-19
4-88
4-83
9-19
10-18
4-83
4-41
10-17
10-19
4-87
2-2
LSB
LSI Logic LCBG10P specifications
luma
luma data filter
luma data output
luma frame store
luma frame store organization
luma interlaced 9-18,
luma letterbox filtering
luma progressive frame 9-17,
luma repositioning
luma value bit
luminance
luminance data See luma data
M
macroblock
macroblock header
main display area 9-5,
main profile @ main level syntax
main reads per line bits
main start/end column bits
main start/end row bits
manufacturing test modes
masks (interrupts) 5-6, 8-20,
mechanical specifications
memory
memory controller See DMA controller
memory devices SDRAM
memory interface
horizontal timing
B frame override
letterbox filtering
repositioning
disabling
location
usage overview
accessing 1-3, 1-5,
buffer allocation
frame store allocation
off-chip writes
OSD storage formats and 9-28,
testing 4-91, 4-92,
arbitration priority
block diagram
channel buffering
decode start delay
overview 1-3,
real-time decoding
reduced memory mode
B-5
B-5
external SDRAM
enable bit
1-5
7-9
9-6
A-2
9-13
9-27
9-20
9-18
4-58
7-1
9-39
7-9
6-9
7-1
7-2
9-17
9-7
A-6
7-6
9-10
9-19
4-68
7-6
7-6
9-19
to
4-93
7-8
7-7
9-18
9-6
5-10
4-70
to
6-27
4-65
7-13
to
7-9
7-3
11-1
2-12
7-8
4-70
7-11
7-8
8-23
to
9-18
7-9
7-13
8-18
11-1
9-29
IX-17