L64105 LSI Logic Corporation, L64105 Datasheet - Page 94

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

4-12
Stream Select [1:0]
SCR Pause
Software Reset
Reserved
Register 8 (0x008)
Register Descriptions
The host must program these bits to set up the L64105
for the format of the input bitstream as shown in the
following table.
Stream
Select [1:0]
0b00
0b01
0b10
0b11
A 0b11 in these bits causes the L64105 to skip packet
searching and byte count matching. Video data is taken
in at the first start code. Subsequent start codes
re-establish the byte alignment. Audio data is not byte
aligned in the channel buffer.
For 0b00 through 0b10, the L64105 parses from the
packet layer and resynchronizes the preparser to the
packet layer start codes on any packet layer errors.
When set, this bit prevents the SCR Counter
from incrementing. However, the SCR Counter can still
be written to by the host (override). When this bit is
cleared, the SCR Counter operates in normal mode, i.e.,
it increments with the system clock. At power-on and
reset, this bit is initialized to 0.
When set by the host, this bit causes the L64105 to reset
(reinitialize). The effect is the same as asserting the hard
reset signal of the chip, RESETn. This reset function
generates a 10-clock cycle reset pulse that resets all
internal modules. All host register values are reinitialized
and need to be reconfigured by the host for proper
operation.
The default value of these bits is 0b11 and should NOT
be overwritten with 0b00.
Reserved
Bitstream Format
A/V PES Packets
MPEG-1 System or MPEG-2
Program Stream
(Not defined)
A/V Elementary Streams
(Figure
R/W [3:2]
R/W 4
[7:6]
[7:0]
4.9)
W 5