L64105 LSI Logic Corporation, L64105 Datasheet - Page 152

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.105 Registers 297–299 (0x129–0x12B) Main Start/End Rows [10:0]
Figure 4.106 Registers 300–302 (0x12C–0x12E) Main Start/End Columns [10:0]
Figure 4.107 Register 303 (0x12F)
4-70
Reg. 297
Reg. 298
Reg. 299
Reg. 300
Reg. 301
Reg. 302
Fcode [8]
MSBs
MSBs
LSB
LSB
LSB
LSB
7
Reserved
Reserved
Vcode Even
Plus 1
7
7
6
The host can write to these registers to program the start and end row
numbers for the Main region on the display. The values entered are the
number of lines from the start of a top or bottom field. Clear bits 7
and 3 in Register 299 when writing to it.
The host can write to these registers to program the start and end
column numbers for the Main region on the display. The values entered
are the number of system clocks from the horizontal sync signal. Clear
bits 7 and 3 in Register 302 when writing to it.
Vcode Zero [4:0]
Register Descriptions
Vcode Even
6
6
Main End Column [10:8]
Main End Row [10:8]
[8]
5
R/W
R/W
The host can write to this field to program the number of
offset lines in the odd/even field beginning from the new
field to the line where the Vcode of the Start of Active
Video/End of Active Video (SAV/EAV) changes from 1
to 0. This the same for both odd and even fields.
4
Main Start Column [7:0]
Main End Column [7:0]
Main Start Row [7:0]
Main End Row [7:0]
4
4
R/W
R/W
R/W
R/W
Reserved
Reserved
3
3
Vcode Zero [4:0]
2
2
Main Start Column [10:8]
Main Start Row [10:8]
R/W
R/W
R/W [4:0]
0
0
0