L64105 LSI Logic Corporation, L64105 Datasheet - Page 183

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 5.6
(Register 17)
Other Events
Divided Clock
Picture Start
Code Event
Code Event
Audio Sync
DTS Video
SCR Pause
(Register 7)
Capture
Mode
Event
...
Operation of the SCR Counter
LSB
In the No Compare and Capture mode, the SCR counter can be read,
paused, and loaded by the host through the SCR Value registers. The
L64105 only keeps the LSB in Register 9 updated. When the host reads
the LSB, the upper three bytes of the counter are captured and written
to Registers 10, 11, and 12. To load a value into the counter, the host
must set the SCR Pause bit in Register 7, write the new counter value
in the SCR Value registers, and then clear the SCR Pause bit. The SCR
counter then increments from the value in the SCR Value registers.
Also in this mode, when the SCR counter overflows, the SCR Overflow
Interrupt bit in Register 1 is set and the INTRn output to the host is
asserted if not masked by the host for this interrupt.
Register Access and Functions
Register 9
LSB
Register 13
Load
SCR Value Registers (R/W)
Register 10
SCR Compare/Capture Registers (R/W)
SCR Temporary Holding
SCR Counter
Register 14
Register 11
LSB
Register 20
Register 15
(Register 17)
(Register 17)
SCR Compare Audio Registers (R/W)
Compare
Compare
Register 12
Register 21
Mode
Mode
Register 16
MSB
MSB
Register 22
Overflow Interrupt
= ?
= ?
(Register 19)
(Register 19)
on Compare
on Compare
Audio Start
Video Start
Register 23
SCR
Compare
Interrupt
MSB
Autostart
Audio
Autostart
Video
5-7